Charge redistribution DACs are common in modern integrated circuits, particularly in switched capacitor CMOS designs. They have uses in many applications, including analog-to-digital (ADC) architectures such as pipeline and successive approximation (SAR) ADCs. Depending on the application, key performance metrics can be the linearity of the DAC and its settling speed.
An exemplary 3-bit charge redistribution DAC 100 is shown in FIG. 1. It is composed of a terminating capacitor 102 and an array of binary-weighted capacitors 104.1, 104.2 and 104.3 with respective capacitances of 1C, 1C, 2C and 4C. The DAC input is a 3 bit binary digital word with each bit controlling a respective switch of the switches 106.1, 106.2 and 106.3 connected to the capacitors. The other side of the switches 106.1, 106.2 and 106.3 is connected to a reference voltage VREF or ground GND depending on the corresponding bit of the DAC input word. Typically, a digital “1” controls a corresponding switch to connect to the reference voltage VREF and a digital “0” controls a corresponding switch to connect to the GND. The DAC output is determined by an equation of Vout=VREF*Cselected/Ctotal, in which Cselected is the amount of capacitance selected by the DAC word, and Ctotal is the sum of all capacitance in the DAC 100. For example, if the DAC code is 101, the capacitors 104.1 and 104.3 are selected by connecting the switches 106.1 and 106.3 to the reference voltage VREF, and the switch 106.2 connects the capacitor 104.2 to the ground GND. The output would be Vout=VREF*(4C+1C)/(4C+2C+1C+1C)=⅝*VREF.
The reference voltage VREF and ground GND have associated parasitics represented by LPAR1 and LPAR2. When any one of the DAC capacitors switches from VREF to GND (or vice versa), the voltage at the DAC output will ring for some period of time, depending on characteristics of the parasitics and capacitance of the DAC 100. In a typical integrated circuit, the ringing phenomenon limits the frequency at which the DAC can be driven.
Thus, at high-speeds, the performance of the DAC is often limited by the parasitics inductance. Accordingly, there is a need to improve the speed at which the charge redistribution DAC settles, in particular for a SAR ADC application.